1. Field of the Invention
The present invention relates to an apparatus for generating and distributing a clock signal of high speed and high precision for a high-speed interface circuit, a processor, and an analog or digital circuit that requires a clock signal of a high frequency.
2. Description of the Related Art
In recent years, frequencies of clock signals have been improving with the rapid advance of semiconductor integrated circuits. As a result, a timing constraint condition required for a clock signal has been becoming strict. Furthermore, with an increase in the scale of an LSI, it is also difficult to distribute a clock signal of high precision to each part within a chip.
An example of a conventional configuration that realizes the distribution of a clock signal is shown in FIG. 1. In the configuration example shown in FIG. 1, a clock signal generated by a PLL (100), which is configured by a voltage control oscillator VCO (50), a frequency divider (60), and a phase comparator PFD/charge pump CP/low-pass filter LF block (70), is transmitted to a circuit block (90) through a clock tree (80) configured by buffers (81). In this example, however, the timing precision and the voltage amplitude of a clock signal degrade while the signal passes through the clock tree (80) where the buffers are provided in a plurality of stages. Especially, this problem is significant in a high-frequency region.
A technique proposed by Patent Document 1 to be described below is shown in FIGS. 2 and 3 as a solution to this problem. In this example, a number of VCOs (51) configured by ring oscillators are arranged in each part within a chip. Oscillation nodes of these VCOs (51) are linked with wire conductors one-dimensionally in FIG. 2 and in a matrix in FIG. 3. Additionally, to control the oscillation frequency of each of the VCOs (51), a control signal generated by a PLL, which is configured by VCOs (51), a frequency divider (60), and a phase comparator PFD/charge pump CP/low-pass filter LF block (70), is distributed to each of the VCOs (51). The apparatus implemented by this technique is hereinafter referred to as a “distributive VCO-type clock generating and distributing apparatus”.
With the distributive VCO-type clock generating and distributing technique shown in FIGS. 2 and 3, a clock signal is generated by the ring oscillators. However, in usual cases, since ring oscillators are susceptible to power noise and the precision of a generated clock signal is low, this technique is not suitable for use in a high-frequency region of several giga hertz or higher.    Patent Document 1: Japanese Published Patent Application No. H11-74762